В. А. Варданян, “О сложности тестов активностей для частичных булевых функций”, Автоматика и телемеханика, Москва, Изд-во Наука, # 7, стр. 118-124, 1986.
В. А. Варданян, “О сложности единичных динамических тестов для монотонных булевых функций”, “Кибернетика”, Киев, Изд-во “Наукова думка”, # 3, стр. 23-26, 1987.
В. А. Варданян, “Об одном методе синтеза легко тестируемых схем”, Автоматика и телемеханика, Москва, Изд-во Наука, # 7, стр. 136-139, 1987.
В. А. Варданян, “О сложности динамических тестов для функций к-значной логики”, “Кибернетика”, Киев, Изд-во “Наукова думка”, # 3, стр. 29-36, 1988.
Shoukourian, V. A. Vardanian, Y. Zorian, SoC yield optimization via an embedded memory test and repair infrastructure, IEEE Design & Test of Computers, vol.21, May-June, 2004, pp. 200-207.
Y. Zorian, G. Torjyan, A. Harutyunyan, V. Vardanian, Apparatus, method, and system to allocate redundant components with subsets of the redundant components, US Patent, No. 7,149,921, USA, 2006.
G. Harutunyan, V. A. Vardanian, Y. Zorian, “Minimal March Tests for Dynamic Faults in Random Access Memories”, Journal of Electronic Testing: Theory and Applications, Vol. 23, Number 1, February 2007, pp. 55-74 (in English).
Aleksanyan K., Amirkhanyan K., Shoukourian S., Vardanian V., Zorian Y., “Memory Modeling Using an Intermediate Level Structural Description”, US Patent, No 7768840, USA, 2010.
K. Aleksanyan, V. A. Vardanian, Y. Zorian, “Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer”, US Patent No. 7890900, USA, 2011.
A. Hakhumyan, G. Harutyunyan, S. Shoukourian, V.A. Vardanian, Y. Zorian, “Symmetry Measure for Memory Test and Its Application in BIST Optimization”, Journal of Electronic Testing : Theory and Applications (JETTA), 2011 , Vol. 27, No. 6, pp.753-766.
Alexanyan K., Amirkhanyan K., Karapetyan S., Shoukourian S., Shubat A., Vardanian V., Zorian Y., “Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers”, US Patent No. 8,112,730, 2012.
G. Harutyunyan, S. Shoukourian, V. Vardanian, Y. Zorian, “A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 6, June 2012, pp. 941-949.
K. Alexanyan, V.A. Vardanian, Y. Zorian, “Various Methods and Apparatuses for Effective Yield Enhancement of Good Chip Dies Having Memories Per Wafer”, US Patent No. 8,359,553, 2013.-18 p.
K. Amirkhanyan, H. Grigoryan, G. Harutyunyan, T. Melkumyan, S. Shoukourian, A. Shubat, V. Vardanian, Y. Zorian, Detecting Random Telegraph Noise Induced Failures In An Electronic Memory, US Patent 8,850,277, 2014.
H. Grigoryan, G. Harutyunyan, S. Shoukourian, V. Vardanian, Y. Zorian, Determining a desirable number of segments for a multi-segment single error correcting coding scheme, US Patent No. 9,053,050, 2015.
|